The present disclosure relates to a solid-state imaging device, a driving method, and an electronic apparatus, and in particular, to a solid-state imaging device, a driving method, and an electronic apparatus allowing an image sensor to obtain natural and beautiful images.
In recent years, CMOS image sensors have been widely used as imaging devices. In addition, CMOS image sensors improved to be more suited to high-speed imaging have also been proposed. For example, a CMOS image sensor has been proposed that uses up/down counters to attain a high frame rate and high resolution without increasing its circuit size (see Japanese Patent Application Laid-open Nos. 2008-103647 and 2005-278135).
In such a CMOS image sensor, the up/down counters perform a down-count operation for the first time and an up-count operation for the second time, thereby automatically performing subtraction processing (a comparison period for the second time—a comparison period for the first time). Then, the polarity of the outputs of comparators is inverted when a reference voltage becomes equal to the signal voltages of column signal lines. With the polarity inversion, the up/down counters stop their counting operations. As a result, the up/down counters hold a count value corresponding to the result of the subtraction processing (the comparison period for the second time—the comparison period for the first time).
By the twice reading operations and the subtraction processing of the up/down counters, an offset component for each ADC is also eliminated in addition to a reset component including fluctuations for each unit pixel. Therefore, only a signal component corresponding to an incident light amount for each unit pixel can be extracted.
Such processing of eliminating a reset component including fluctuations for each unit pixel is so-called CDS (Correlated Double Sampling) processing.
A period where the up/down counters perform the down-count operation is called a P-phase (Reset Phase) period, and a period where the up/down counters perform the up-count operation is called a D-phase (Data Phase) period.
However, in a case where the pixels of the CMOS image sensor are irradiated with high illumination light such as sunlight, charges photoelectrically converted by photodiodes may leak to floating diffusions.
In such a case, it is difficult to accurately count the reset components of the pixels. Therefore, the up/down counters fully count a clock signal in the P-phase period (i.e., countdown to a limit).
Then, because the difference between the count value of the clock signal in the P-phase period and that of the clock signal in the D-phase period becomes small, output values representing pixel signals also become small. As a result, a phenomenon occurs where the pixels to be displayed in, for example, white (bright color) are displayed in black. Such a phenomenon is also called a blackening phenomenon.
In order to prevent the blackening phenomenon, there have been taken some measures from the past. According to one measure, the count value of the clock signal in the P-phase period is monitored to set flags to the pixels where the blackening phenomenon may occur, and the count value of the clock signal in the D-phase period of the pixels is uniformly corrected to a maximum value.